In a typical integrated circuit (IC) computer-assisted design (CAD) process, a layout version of the design may be drawn or generated. As is well known in the art, the layout is often separated into layers corresponding to the different layers used in manufacturing and further organized into levels of hierarchy, corresponding, for instance, to levels of abstraction in the architectural version of the design. The layout version of the design generally consists of polygons restricted in placement and dimension by specific design rules. Most polygons in the layout represent a component of some structure to be implemented on the layer associated with the polygon. In a typical example, an n-p-n transistor in a CMOS design may be represented by two rectangles representing n-type diffusions in a p substrate, each implementing a source/drain of the transistor, and a rectangle representing the polysilicon gate.
One step in the analysis of a design in the layout version may require physical properties of the final manufactured circuit to be deduced from the layout version by an extraction CAD tool. In one instance, polygons representing conductive portions of the IC may be analyzed with respect to their geometries to construct a resistor network corresponding to the circuit the polygons represent, a process known in the art as resistance extraction. However, because polygons that form a circuit on a layer of the design may be drawn at different times in different layers of the hierarchy, some pre-processing of the polygons must be performed in order to eliminate overlaps and optimize the polygons for extraction by reorganizing them into a geometrically equivalent set of polygons that are better suited for extraction purposes.